A known brushless motor drive circuit as disclosed in Japanese Patent Disclosure No. 58-93482 typically comprises two-phase drive coils for rotatively driving a rotor magnet and a pair of Hall devices for detecting the rotary position of the rotor magnet, a pair of amplifying means for respectively amplifying output signals from the Hall devices, a pair of controlling and multiplying means for multiplying the respective outputs by a reference voltage, output signals from the controlling and multiplying means for controlling the operation of the drive coils, and squaring means for squaring the output voltages being applied to the two-phase drive coils and for feeding back the product of the squarings to the Hall devices.
Another known brushless motor drive circuit as illustrated in FIG. 9 comprises a rotor magnet 1 having 2n (n=integer) magnetized poles, 3-phase drive coils 2, 3, 4 for rotatively driving said rotor magnet 1 and locating means 5, 6 operated by a given electric current supplied from a power source 7 for locating the rotary position of the rotor magnet 1 by detecting the magnetic fields .phi.u, .phi.v of the rotor magnet 1. Amplifying means 8, 9 amplify output signals from the Hall devices 5, 6 and synthesizing means 10 adds and inverts the output signals U, V of the respective amplifying means 8, 9 to synthetically form a signal W=-(U+V) having a third phase. Controlling and multiplying means 11, 12 13 respectively multiply the output signals U, V and W by a speed control signal CTL and the products of the multiplications are respectively amplified by output amplifying means 14, 15, 16 before they are respectively fed to 3-phase drive coils 2, 3, 4. The output signals U and V of the amplifying means 8, 9 and the output signal W of the synthesizing means 10 are respectively and repeatedly multiplied by themselves in repetitively multiplying operation means 17, 18, 19, an even number being provided as exponent for the repeated multiplications so that the sum of the products becomes equal to a given value. In control section 20, output signals U.sup.2, V.sup.2 and W.sup.2 of the repetitively multiplying operation means 17, 18, 19 are added by adder 21 and the output signal of the adder 21 is compared with reference voltage REF by comparator 22 and an error signal, if any, is fed back to the amplifying means 8, 9 which function as so many multipliers and amplifiers. The feedback loop system controls the gain of the amplifying means in such a manner that the relationship U.sup.2 +V.sup.2 +W.sup.2 =REF is always maintained. This prior approach is disclosed in U.S. Pat. No. 4,658,190.